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19-3185; Rev 3; 3/09
256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
General Description
The MAX5417/MAX5418/MAX5419 nonvolatile, lineartaper, digital potentiometers perform the function of a mechanical potentiometer by replacing the mechanics with a simple 2-wire digital interface, allowing communication with multiple devices. Each device performs the same function as a discrete potentiometer or variable resistor and has 256 tap points. The devices feature an internal, nonvolatile EEPROM used to store the wiper position for initialization during power-up. The fast-mode I2C-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnection complexity in many applications. Each device is available with one of four factory-preset addresses (see the Selector Guide) and features an address input for a total of eight unique address combinations. The MAX5417/MAX5418/MAX5419 provide three nominal resistance values: 50k (MAX5417), 100k (MAX5418), or 200k (MAX5419). The nominal resistor temperature coefficient is 35ppm/C end-to-end, and only 5ppm/C ratiometric. This makes the devices ideal for applications requiring a low-temperature-coefficient variable resistor, such as low-drift, programmable gainamplifier circuit configurations. The MAX5417/MAX5418/MAX5419 are available in a 3mm x 3mm 8-pin TDFN package, and are specified over the extended -40C to +85C temperature range.
Features
Power-On Recall of Wiper Position from Nonvolatile Memory Tiny 3mm x 3mm 8-Pin TDFN Package 35ppm/C End-to-End Resistance Temperature Coefficient 5ppm/C Ratiometric Temperature Coefficient 50k/100k/200k Resistor Values Fast I2C-Compatible Serial Interface 500nA (typ) Static Supply Current Single-Supply Operation: +2.7V to +5.25V 256 Tap Positions 0.5 LSB DNL in Voltage-Divider Mode 0.5 LSB INL in Voltage-Divider Mode
MAX5417/MAX5418/MAX5419
Functional Diagram
H VDD GND 8-BIT SHIFT REGISTER 8 8-BIT 8 LATCH 256256 POSITION DECODER W L SDA SCL A0 I2C INTERFACE POR 8-BIT NV MEMORY
Applications
Mechanical Potentiometer Replacement Low-Drift Programmable-Gain Amplifiers Volume Control Liquid-Crystal Display (LCD) Contrast Control
MAX5417 MAX5418 MAX5419
Ordering Information/Selector Guide
PART MAX5417LETA MAX5417META* MAX5417NETA* MAX5417PETA* MAX5418LETA MAX5418META* MAX5418NETA* MAX5418PETA* MAX5419LETA MAX5419META* MAX5419NETA* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C I C ADDRESS 010100A0 010101A0 010110A0 010111A0 010100A0 010101A0 010110A0 010111A0 010100A0 010101A0 010110A0 010111A0
2
R (k) 50 50 50 50 100 100 100 100 200 200 200 200
PIN-PACKAGE 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP** 8 TDFN-EP**
TOP MARK AIB ALS ALT ALU AIC ALV ALW ALX AID ALY ALZ AMA
MAX5419PETA* -40C to +85C *Future product--contact factory for availability. **Exposed pad.
Pin Configuration appears at end of data sheet.
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________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Maximum Continuous Current into H, L, and W MAX5417......................................................................1.3mA MAX5418......................................................................0.6mA MAX5419......................................................................0.3mA Continuous Power Dissipation (TA = +70C) 8-Pin TDFN (derate 24.4mW/C above +70C) .........1951mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, H = VDD, L = GND, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.)
PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity End-to-End Temperature Coefficient Ratiometric Temperature Coefficient Full-Scale Error MAX5417_, 50 MAX5418_, 100k MAX5419_, 200k MAX5417_, 50k Zero-Scale Error MAX5418_, 100k MAX5419_, 200k VDD = 3V VDD = 5V VDD = 3V, MAX5417_, 50k, guaranteed monotonic Differential Nonlinearity (Note 2) DNL VDD = 3V, MAX5418_, 100k MAX5419_, 200k VDD = 5V DC PERFORMANCE (RESISTOR CHARACTERISTICS) Wiper Resistance Wiper Capacitance End-to-End Resistance RW CW MAX5417_ RHL MAX5418_ MAX5419_ 37.5 75 150 VDD = 3V to 5.25V (Note 3) 325 10 50 100 200 62.5 125 250 k 675 pF -1 INL DNL TCR (Note 1) (Note 1) 35 5 -0.6 -0.3 -0.15 0.6 0.3 0.15 3 1.5 +2 1 1 1 LSB LSB SYMBOL CONDITIONS MIN 256 0.5 0.5 TYP MAX UNITS Taps LSB LSB ppm/C ppm/C
DC PERFORMANCE (VOLTAGE-DIVIDER MODE)
LSB
DC PERFORMANCE (VARIABLE-RESISTOR MODE) Integral Nonlinearity (Note 2) INL LSB
2
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, H = VDD, L = GND, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.)
PARAMETER DIGITAL INPUTS Input High Voltage (Note 4) Input Low Voltage Low-Level Output Voltage Input Leakage Current Input Capacitance DYNAMIC CHARACTERISTICS MAX5417_ Wiper -3dB Bandwidth (Note 5) NONVOLATILE MEMORY Data Retention Endurance POWER SUPPLY Power-Supply Voltage Standby Current Programming Current VDD IDD Digital inputs = VDD or GND, TA = +25C During nonvolatile write; digital inputs = VDD or GND (Note 6) 2.70 0.5 200 5.25 1 400 V A A TA = +85C TA = +25C TA = +85C 50 200,000 50,000 Years Stores MAX5418_ MAX5419_ 100 50 25 kHz VIH VIL VOL ILEAK 5 VDD = 3.4V to 5.25V VDD < 3.4V VDD = 2.7V to 5.25V (Note 4) 3mA sink current 2.4 0.7 x VDD 0.8 0.4 1 V V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5417/MAX5418/MAX5419
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, H = VDD, L = GND, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C. See Figures 1 and 2.) (Note 7)
PARAMETER ANALOG SECTION MAX5417_ Wiper Settling Time (Note 8) DIGITAL SECTION SCL Clock Frequency Setup Time for START Condition Hold Time for START Condition CLK High Time CLK Low Time fSCL tSU-STA tHD-STA tHIGH tLOW 0.6 0.6 0.6 1.3 400 kHz s s s s tIL MAX5418_ MAX5419_ 500 600 1000 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
TIMING CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, H = VDD, L = GND, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C. See Figures 1 and 2.) (Note 7)
PARAMETER Data Setup Time Data Hold Time SDA, SCL Rise Time SDA, SCL Fall Time Setup Time for STOP Condition Bus Free Time Between STOP and START Condition Pulse Width of Spike Suppressed Maximum Capacitive Load for Each Bus Line Write NV Register Busy Time SYMBOL tSU-DAT tHD-DAT tR tF tSU-STO tBUF tSP CB tBUSY (Note 9) (Note 10) 400 12 Minimum power-up rate = 0.2V/ms 0.6 1.3 50 CONDITIONS MIN 100 0 0.9 300 300 TYP MAX UNITS ns s ns ns s s ns pF ms
Note 1: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDD and L = GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter. Note 2: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = GND. For the 5V condition, the wiper terminal is driven with a source current of 80A for the 50k configuration, 40A for the 100k configuration, and 20A for the 200k configuration. For the 3V condition, the wiper terminal is driven with a source current of 40A for the 50k configuration, 20A for the 100k configuration, and 10A for the 200k configuration. Note 3: The wiper resistance is measured using the source currents given in Note 2. For operation to VDD = 2.7V, see Wiper Resistance vs. Temperature in the Typical Operating Characteristics. Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 5: Wiper at midscale with a 10pF load (DC measurement). L = GND; an AC source is applied to H; and the W output is measured. A 3dB bandwidth occurs when the AC W/H value is 3dB lower than the DC W/H value. Note 6: The programming current operates only during power-up and NV writes. Note 7: SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed from a voltage level of (VIL + VIH) / 2. Note 8: Wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. H = VDD, L = GND, and the wiper terminal is unloaded and measured with a 10pF oscilloscope probe (see the Typical Operating Characteristics for the tap-to-tap switching transient). Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. Note 10: The idle time begins from the initiation of the stop pulse.
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
MAX5417/MAX5418/MAX5419
DNL vs. TAP POSITION
MAX5417 toc01
INL vs. TAP POSITION
MAX5417 toc02
WIPER RESISTANCE vs. TAP POSITION
VDD = 2.7V ISRC = 50A
MAX5417 toc03
0.25 0.20 0.15 RESISTANCE DNL (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0 32 64 96 VOLTAGE-DIVIDER MODE
0.25 0.20 0.15 RESISTANCE INL (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 VOLTAGE-DIVIDER MODE
700 600 RESISTANCE () 500 400 300 200 100 0
128 160 192 224 256
0
32
64
96
128 160 192 224 256
0
32
64
96
128 160 192 224 256
TAP POSITION
TAP POSITION
TAP POSITION
WIPER TRANSIENT AT POWER-ON
MAX5417 toc04
END-TO-END RESISTANCE % CHANGE vs. TEMPERATURE
END-TO-END RESISTANCE % CHANGE 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -15 10 35 60 85
MAX5417 toc05
VDD 2V/div
1.0
W 1V/div
CL = 10pF TAP = 128 H = VDD 4s/div
TEMPERATURE (C)
STANDBY SUPPLY CURRENT vs. TEMPERATURE
MAX5417 toc06
WIPER RESISTANCE vs. TEMPERATURE
MAX5417 toc07
1.0 STANDBY SUPPLY CURRENT (A)
700 600 RESISTANCE () 500 400 300 200 VDD = 2.7V VDD = 3.0V VDD = 4.5V VDD = 5.25V
0.8
0.6
0.4
0.2
100 0 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
0
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
Typical Operating Characteristics (continued)
(VDD = +5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
MAX5417 toc08
THD+N RESPONSE
MAX5417 toc09
INL vs. TAP POSITION (MAX5417)
2.5 RESISTANCE INL (LSB) 2.0 1.5 1.0 0.5 0 VARIABLE-RESISTOR MODE VDD = 2.7V ISRC = 50A
MAX5417 toc10
600 500 SUPPLY CURRENT (A) 400 300 200 100 0 0 1 2 3 4 5 DIGITAL INPUT VOLTAGE (V)
100 10 1 THD+N (%) 0.1 0.01 0.001 0.0001 10 100 1k FREQUENCY (Hz) 10k 1:1 RATIO 20Hz TO 20kHz BANDPASS
3.0
-0.5 -1.0 100k 0 32 64 96 128 160 192 224 256 TAP POSITION
INL vs. TAP POSITION (MAX5418)
VARIABLE-RESISTOR MODE VDD = 2.7V ISRC = 20A
MAX5417 toc11
INL vs. TAP POSITION (MAX5419)
0.75 0.50 VARIABLE-RESISTOR MODE VDD = 2.7V ISRC = 10A
MAX5417 toc12 MAX5417 toc14
2.0 1.5 1.0 INL (LSB)
1.00
INL (LSB)
0.25 0 -0.25 -0.50
0.5 0 -0.5 -1.0 0 32 64 96 128 160 192 224 256 TAP POSITION
-0.75 -1.00 0 32 64 96 128 160 192 224 256 TAP POSITION
DNL vs. TAP POSITION (MAX5417)
VARIABLE-RESISTOR MODE 0.4 0.3 DNL (LSB) DNL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 0 32 64 96 128 160 192 224 256 TAP POSITION -0.2 -0.3 0 32 0.1 0 -0.1
MAX5417 toc13
DNL vs. TAP POSITION (MAX5418)
0.3 0.2 VARIABLE-RESISTOR MODE VDD = 2.7V ISRC = 20A
0.5
64
96
128 160 192 224 256
TAP POSITION
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
Typical Operating Characteristics (continued)
(VDD = +5V, TA = +25C, unless otherwise noted.)
DNL vs. TAP POSITION (MAX5419)
MAX5417 toc15
MAX5417/MAX5418/MAX5419
MIDSCALE WIPER RESPONSE vs. FREQUENCY (MAX5417)
MAX5417 toc16
MIDSCALE WIPER RESPONSE vs. FREQUENCY (MAX5418)
MAX5418 TAP = 128 CL = 10pF -10 -15 CL = 50pF -20 -25 -30
MAX5417 toc17
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3 0 32 64 96 VARIABLE-RESISTOR MODE VDD = 2.7V ISRC = 10A
0 -5 WIPER RESPONSE (dB) -10 -15 -20 -25 -30
MAX5417 TAP = 128 CL = 10pF
0 -5 WIPER RESPONSE (dB)
CL = 50pF
128 160 192 224 256
1
10
100
1000
1
10
100
1000
TAP POSITION
FREQUENCY (kHz)
FREQUENCY (kHz)
MIDSCALE WIPER RESPONSE vs. FREQUENCY (MAX5419)
-5 -10 WIPER RESPONSE (dB) -15 -20 -25 -30 -35 -40 -45 1 10 100 1000 CL = 50pF MAX5419 TAP = 128 CL = 10pF
MAX5417 toc18
TAP-TO-TAP SWITCHING TRANSIENT (MAX5417)
MAX5417 toc19
0
SDA 2V/div
MAX5417 CL = 10pF FROM TAP 127 TO TAP 128 H = VDD 1s/div
W 10mV/div
FREQUENCY (kHz)
TAP-TO-TAP SWITCHING TRANSIENT (MAX5418)
MAX5417 toc20
TAP-TO-TAP SWITCHING TRANSIENT (MAX5419)
MAX5417 toc21
SDA 2V/div W 10mV/div MAX5418 CL = 10pF FROM TAP 127 TO TAP 128 H = VDD 1s/div 1s/div MAX5419 CL = 10pF FROM TAP 127 TO TAP 128 H = VDD
SDA 2V/div W 10mV/div
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
Pin Description
PIN 1 2 3 4 5 6 7 8 -- NAME VDD SCL SDA A0 GND L W H EP I2C-Interface Clock Input I2C-Interface Data Input Address Input. Sets the A0 bit in the device ID address. Ground Low Terminal Wiper Terminal High Terminal Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical point. FUNCTION Power-Supply Input. 2.7V to 5.25V voltage range. Bypass with a 0.1F capacitor from VDD to GND.
tR SDA tSU-DAT tLOW SCL tHD-STA tR S PARAMETERS ARE MEASURED FROM 30% TO 70%. tHIGH tF Sr A P tHD-DAT tHD-STA tBUF tSU-STO
tF
tSU-STA
S
Figure 1. I2C Serial-Interface Timing Diagram
Detailed Description
VDD IOL = 3mA
SDA
VOUT 400pF
IOH = 0mA
The MAX5417/MAX5418/MAX5419 contain a resistor array with 255 resistive elements. The MAX5417 has a total end-to-end resistance of 50k, the MAX5418 has an end-to-end resistance of 100k, and the MAX5419 has an end-to-end resistance of 200k. The MAX5417/MAX5418/MAX5419 allow access to the high, low, and wiper terminals for a standard voltage-divider configuration. H, L, and W can be connected in any desired configuration as long as their voltages fall between GND and VDD. A simple 2-wire I2C-compatible serial interface moves the wiper among the 256 tap points. A nonvolatile memory stores the wiper position and recalls the stored wiper position in the nonvolatile memory upon power-up. The nonvolatile memory is guaranteed for 50 years for wiper data retention and up to 200,000 wiper store cycles.
Figure 2. Load Circuit
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
Analog Circuitry
The MAX5417/MAX5418/MAX5419 consist of a resistor array with 255 resistive elements; 256 tap points are accessible to the wiper, W, along the resistor string between H and L. The wiper tap point is selected by programming the potentiometer through the 2-wire (I2C) interface. Eight data bits, an address byte, and a control byte program the wiper position. The H and L terminals of the MAX5417/MAX5418/MAX5419 are similar to the two end terminals of a mechanical potentiometer. The MAX5417/MAX5418/MAX5419 feature power-on reset circuitry that loads the wiper position from nonvolatile memory at power-up.
Digital Interface
The MAX5417/MAX5418/MAX5419 feature an internal, nonvolatile EEPROM that stores the wiper state for initialization during power-up. The shift register decodes the control and address bits, routing the data to the proper memory registers. Data can be written to a volatile memory register, immediately updating the wiper position, or data can be written to a nonvolatile register for storage. The volatile register retains data as long as the device is powered. Once power is removed, the volatile register is cleared. The nonvolatile register retains data even after power is removed. Upon power-up, the power-on reset circuitry controls the transfer of data from the nonvolatile register to the volatile register.
Serial Addressing The MAX5417/MAX5418/MAX5419 operate as a slave that receives data through an I2C- and SMBusTM-compatible 2-wire interface. The interface uses a serial data access (SDA) line and a serial clock line (SCL) to achieve communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to the MAX5417/MAX5418/MAX5419, and generates the SCL clock that synchronizes the data transfer (Figure 1). The MAX5417/MAX5418/MAX5419 SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on the SDA bus. The MAX5417/MAX5418/MAX5419 SCL operates only as an input. A pullup resistor, typically 4.7k, is required on the SCL bus if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START (S) condition (Figure 3) sent by a master, followed by the MAX5417/MAX5418/MAX5419 7-bit slave address plus the 8th bit (Figure 4), 1 command byte (Figure 7) and 1 data byte, and finally a STOP (P) condition (Figure 3). Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3). Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high (Figure 5).
MAX5417/MAX5418/MAX5419
SDA
SCL S START CONDITION P STOP CONDITION
Figure 3. Start and Stop Conditions
SDA
0 MSB
1
0
1
0*
0*
A0 LSB
NOP/W
ACK
SCL *See the Ordering Information/Selector Guide section for other address options.
Figure 4. Slave Address SMBus is a trademark of Intel Corporation.
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
Table 1. MAX5417/MAX5418/MAX5419 Address Codes
ADDRESS BYTE PART SUFFIX L L M M N N P P A6 0 0 0 0 0 0 0 0 A5 1 1 1 1 1 1 1 1 A4 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 NOP/W NOP/W NOP/W NOP/W NOP/W NOP/W NOP/W NOP/W NOP/W
Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 6). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5417/MAX5418/MAX5419, the devices generate the acknowledge bit because the MAX5417/MAX5418/ MAX5419 are the recipients. Slave Address The MAX5417/MAX5418/MAX5419 have a 7-bit-long slave address (Figure 4). The 8th bit following the 7-bit
slave address is the NOP/W bit. Set the NOP/W bit low for a write command and high for a no-operation command. The MAX5417/MAX5418/MAX5419 are available in one of four possible slave addresses (Table 1). The first 4 bits (MSBs) of the MAX5417/MAX5418/MAX5419 slave addresses are always 0101. The next 2 bits are factory programmed (see Table 1). Connect the A0 input to either GND or V DD to toggle between two unique device addresses for a part. Each device must have a unique address to share the bus. Therefore, a maximum of eight MAX5417/MAX5418/MAX5419 devices can share the same bus.
SDA
START CONDITION SCL 1 2
CLOCK PULSE FOR ACKNOWLEDGMENT
8 NOT ACKNOWLEDGE
9
SCL SDA DATA STABLE, DATA VALID CHANGE OF DATA ALLOWED ACKNOWLEDGE
Figure 5. Bit Transfer
Figure 6. Acknowledge
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX5417/MAX5418/MAX5419 S SLAVE ADDRESS NOP/W 0 A
D15
D14
D13
D12
D11
D10
D9
D8
CONTROL BYTE ACKNOWLEDGE FROM MAX5417/MAX5418/MAX5419
A
P
Figure 7. Command Byte Received
HOW CONTROL BYTE AND DATA BYTE MAP INTO MAX5417/MAX5418/MAX5419 REGISTERS ACKNOWLEDGE FROM MAX5417/MAX5418/MAX5419 S SLAVE ADDRESS NOP/W 0 A
ACKNOWLEDGE FROM MAX5417/MAX5418/MAX5419 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
ACKNOWLEDGE FROM MAX5417/MAX5418/MAX5419 D5 D4 D3 D2 D1 D0
CONTROL BYTE
A
DATA BYTE 1 BYTE
A
P
Figure 8. Command and Single Data Byte Received
Message Format for Writing
A write to the MAX5417/MAX5418/MAX5419 consists of the transmission of the device's slave address with the 8th bit set to zero, followed by at least 1 byte of information (Figure 7). The 1st byte of information is the command byte. The bytes received after the command byte are the data bytes. The 1st data byte goes into the internal register of the MAX5417/MAX5418/MAX5419 as selected by the command byte (Figure 8).
Command Descriptions VREG: The data byte writes to the volatile memory register and the wiper position updates with the data in the volatile memory register. NVREG: The data byte writes to the nonvolatile memory register. The wiper position is unchanged.
NVREGxVREG: Data transfers from the nonvolatile memory register to the volatile memory register (wiper position updates). VREGxNVREG: Data transfers from the volatile memory register into the nonvolatile memory register.
Command Byte Use the command byte to select the source and destination of the wiper data (nonvolatile or volatile memory registers) and swap data between nonvolatile and volatile memory registers (see Table 2).
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
Table 2. Command Byte Summary
ADDRESS BYTE SCL CYCLE NUMBER VREG NVREG NVREGxVREG VREGxNVREG 1 2 3 A4 0 0 0 0 4 A3 1 1 1 1 5 6 7 A0 A0 A0 A0 A0 0 0 0 0 8 9 ACK 0 0 0 0 10 11 TX 0 0 1 1 CONTROL BYTE 12 NV 0 1 1 0 13 V 1 0 0 1 14 R3 0 0 0 0 15 R2 0 0 0 0 16 R1 0 0 0 0 17 R0 1 1 1 1 18 ACK 19 D7 D7 D7 X X 20 D6 D6 D6 X X 21 D5 D5 D5 X X DATA BYTE 22 D4 D4 D4 X X 23 D3 D3 D3 X X 24 D2 D2 D2 X X 25 D1 D1 D1 X X 26 D0 D0 D0 X X 27 ACK P S
A6 A5 0 0 0 0 1 1 1 1
A2 A1 A2 A1 A2 A1 A2 A1 A2 A1
X = Don't care.
Nonvolatile Memory
The internal EEPROM consists of an 8-bit nonvolatile register that retains the value written to it before the device is powered down. The nonvolatile register is programmed with the midscale value at the factory.
Positive LCD Bias Control
Figures 9 and 10 show an application where the voltage-divider or variable resistor is used to make an adjustable, positive LCD bias voltage. The op amp provides buffering and gain to the resistor-divider network made by the potentiometer (Figure 9) or to a fixed resistor and a variable resistor (see Figure 10).
Power-Up
Upon power-up, the MAX5417/MAX5418/MAX5419 load the data stored in the nonvolatile memory register into the volatile memory register, updating the wiper position with the data stored in the nonvolatile memory register. This initialization period takes 10s.
Programmable Filter
Figure 11 shows the configuration for a 1st-order programmable filter. The gain of the filter is adjusted by R2, and the cutoff frequency is adjusted by R3. Use the following equations to calculate the gain (G) and the 3dB cutoff frequency (fC): R1 R2 1 fC = 2 x R3 x C G = 1+
Standby
The MAX5417/MAX5418/MAX5419 feature a low-power standby. When the device is not being programmed, it goes into standby mode and power consumption is typically 500nA.
Applications Information
The MAX5417/MAX5418/MAX5419 are intended for circuits requiring digitally controlled adjustable resistance, such as LCD contrast control (where voltage biasing adjusts the display contrast), or for programmable filters with adjustable gain and/or cutoff frequency.
5V 5V H 30V MAX5417 MAX5418 MAx5419 L W VOUT MAX5417 MAX5418 MAX5419 L H VOUT 30V
W
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
12
Figure 10. Positive LCD Bias Control Using a Variable Resistor
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256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
W
5V
VIN L H R3 C VOUT
7
R1
MAX5417 MAX5418 MAX5419 1 8 6
MAX410
3
H MAX5417 MAX5418 MAX5419
2 W 4 -5V R2 R1 H
R2
W
L
L
Figure 11. Programmable Filter
Figure 13. Offset Voltage and Gain Adjustment Circuit
+5V VIN OUT H MAX6160 ADJ MAX5417 MAX5418 MAX5419 GND W VDD 1 SCL 2 L SDA 3 A0 4 V0 = 1.23V 50k FOR THE MAX5417 R2(k) V0 = 1.23V 100k FOR THE MAX5418 R2(k) 200k FOR THE MAX5419 V0 = 1.23V R2(k) V0 REF
Pin Configuration
TOP VIEW
8H 7W
MAX5417 MAX5418 MAX5419
6L 5 GND
TDFN
Figure 12. Adjustable Voltage Reference
Adjustable Voltage Reference
Figure 12 shows the MAX5417/MAX5418/MAX5419 used as the feedback resistors in multiple adjustable voltagereference applications. Independently adjust the output voltage of the MAX6160 from 1.23V to VIN - 0.2V by changing the wiper positions of the MAX5417/ MAX5418/MAX5419. PROCESS: BiCMOS
Chip Information
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 8 TDFN-EP PACKAGE CODE T833-1 DOCUMENT NO. 21-0137
Offset Voltage and Gain Adjustment
Connect the high and low terminals of one potentiometer of a MAX5417 between the NULL inputs of a MAX410 and the wiper to the op amp's positive supply to nullify the offset voltage over the operating temperature range. Install the other potentiometer in the feedback path to adjust the gain of the MAX410 (see Figure 13).
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13
256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers MAX5417/MAX5418/MAX5419
Revision History
REVISION NUMBER 0 1 3 3 REVISION DATE 2/04 4/04 2/04 3/09 Initial release Adding future product Adding new part Changes to add details about exposed pad, corrections to Table 2, style edits DESCRIPTION PAGES CHANGED -- -- -- 1, 8, 12-15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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